Subject: Re: k0/k1 register while mulhi/mullo manipulation
To: None <,>
From: Michael L. Hitch <>
List: port-mips
Date: 02/23/2000 06:11:46
On Wed, 23 Feb 2000, Toru Nishimura wrote:

> Now, I could build another, more likely, reasoning why recent
> NetBSD/pmax kernels (1.4T) lock up sporadorically; an unexpected
> interrupt during critical section.  Let see following locore_mips1.S
> change;
> +       lw      k0, TF_BASE+TF_REG_EPC(sp)
>         mtc0    a0, MIPS_COP_0_STATUS
>         mtlo    t0
>         mthi    t1
> -       lw      k0, TF_BASE+TF_REG_EPC(sp)
>         ...
>         j       k0
> 	rfe
> The 'mtc0 a0, ...' insn has the effect to make sure no more interrupt.
> But if the new code sequence got an interrupt after 'lw k0, ...'
> before 'mtc0 a0, ...', k0 would be trashed by the interrupt handler
> (not by mtlo/mthi insns) and glok in a hidious way.  How is this
> senario?

  I think is is very likely, and I also have seen some comments in the
code that indicate that it may take 1 or 2 clock cycles after the mtc0
instruction before the interrrupts are actually disabled (but I don't
know of any documented information on that).

  I have no idea why Charles moved that load of k0 like that.> 

Michael L. Hitch
Computer Consultant
Information Technology Center
Montana State University	Bozeman, MT	USA