> > My vague memory whispers me 'k0/k1 contents might be trashed under certain
> > circumstances, e.g., after calling mt*/mf* for mulhi/mullo'.
> "(Even) when CPU is running kernel mode and no TLB miss is expected,"

If you have any kind of interrupts enabled, then k0/k1 are off limits.
One of them might be overwritten by an interrupt return address at any
time, and the other might be zero'd or whatever the interrupt handler
does to cover its tracks.

Of all the R3xxx/R4xxx docs and chips I've dealt with, there was never any
warning that k0/k1 could be trashed by hardware. They really are general
purpose registers, but (nearly?) all MIPS systems reserve them for interrupt
handling code to use. MIPS interrupt handling hardware is extremely minimal
and that is what requires at least one general register to be trashed by
interrupt handlers no matter what (they can't return without it).

As for the HI/LO registers, there are plenty of warnings about touching
HI/LO during the two cycles after MFHI/MFLO. So if you are doing another
multiply or divide too close to the previous MFHI/MFLO, you will get
trashing of the value in the HI/LO register. Could this be it?

Todd Whitesel
toddpw @ best.com