Subject: Re: k0/k1 register while mulhi/mullo manipulation
To: None <port-mips@netbsd.org, port-pmax@netbsd.org>
From: Toru Nishimura <nisimura@itc.aist-nara.ac.jp>
List: port-mips
Date: 02/23/2000 20:29:53
I noticed my failure to mention to an important point. PLS add,
"(Even) when CPU is running kernel mode and no TLB miss is expected,"
> My vague memory whispers me 'k0/k1 contents might be trashed under certain
> circumstances, e.g., after calling mt*/mf* for mulhi/mullo'. I can not
> remember where I got the knowledge, and I might be wrong.
Tohru Nishimura