Subject: k0/k1 register while mulhi/mullo manipulation To: None <port-mips@netbsd.org, port-pmax@netbsd.org> From: Toru Nishimura <nisimura@itc.aist-nara.ac.jp> List: port-mips Date: 02/23/2000 19:39:38
I'm wondering whether there is a constraint in k0/k1 register contents
while manipulating mulhi/mullo registers via mt*/mf* operations. Can
someone assert/deny my suspiction?
Tohru Nishimura
Nara Institute of Science and Technology