Subject: Re: CPU specific idle routine
To: Toru Nishimura <nisimura@itc.aist-nara.ac.jp>
From: Warner Losh <imp@village.org>
List: port-mips
Date: 01/17/2000 18:38:38
In message <200001180045.JAA01554@axp46.aist-nara.ac.jp> Toru Nishimura writes:
: "It's the way of kitchen sink," I believe.  You need global design sense
: beyond solving in-the-place issues.

Yes.  That's true.

: Take a look at sparc or arm32 about processor encapsulations.
: Primitives depending designs and parameters could be treated in a
: similar way.  Wiredown handlers are of subject.  Taking locore
: routines into parts should be considered carefully as it'd be easily
: result in tangled codes.

One cool thing that Linux did was to have an optimized assembler
routine for each mips processor that was then becopied to the trap
handler address for tlb miss, etc.  That way the number of tlb entries 
could be wired in place and you'd save a load or two in the tlb
routnies.  You could also put really oddball silicon bug workarounds
there as well for very specific models and have a kernel that ran on
multiple machines w/o recompilation.

Warner