Subject: TX3912/3922 support
To: None <port-mips@netbsd.org>
From: UCHIYAMA Yasushi <uch@nop.or.jp>
List: port-mips
Date: 11/21/1999 19:23:03
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To support TX3912/TX3922 based hpcmips machine, attached patch is
required.
I want to apply this patch. OK?
mips/include/cpuregs.h
mips/include/r3900regs.h
mips/mips/db_interface.c
mips/mips/locore.S
mips/mips/locore_mips1.S
mips/mips/mips_machdep.c
... R3900,R3920 cache system is different from R3000A's one.
mips/include/vmparam.h
... system address map change (exclude R3900 reserved area)
mips/mips/pmap.c
... TX3912,TX3922 device I/O region lies 0x6c000000-0x7c000000
options KSEG2IOBUFSIZE reserves PTE entry for this area.
---
UCHIYAMA Yasushi
uch@nop.or.jp
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Content-Description: mips-tx.patch
diff -x CVS -urN mips.orig/include/cpuregs.h mips/include/cpuregs.h
--- mips.orig/include/cpuregs.h Sat Sep 25 09:00:37 1999
+++ mips/include/cpuregs.h Sat Oct 30 22:46:16 1999
@@ -647,4 +647,8 @@
#define MIPS_R3TOSH 0x22 /* ? Toshiba R3000 based FPU ISA I */
#define MIPS_R3NKK 0x23 /* ? NKK R3000 based FPU ISA I */
+#ifdef ENABLE_MIPS_TX3900
+#include <mips/r3900regs.h>
+#endif
+
#endif /* _MIPS_CPUREGS_H_ */
diff -x CVS -urN mips.orig/include/r3900regs.h mips/include/r3900regs.h
--- mips.orig/include/r3900regs.h Thu Jan 1 09:00:00 1970
+++ mips/include/r3900regs.h Sun Nov 21 18:36:06 1999
@@ -0,0 +1,143 @@
+/* $NetBSD$ */
+
+/*
+ * Copyright (c) 1999, by UCHIYAMA Yasushi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the developer may NOT be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+/*
+ * [address space]
+ * kseg2 0xc0000000 - 0xfeffffff
+ * reserved 0xff000000 - 0xfffeffff
+ * kseg2 0xffff0000 - 0xffffffff
+ * -> vmparam.h VM_MAX_KERNEL_ADDRESS
+ */
+
+/*
+ * [cause register]
+ */
+#define R3900_CR_EXC_CODE MIPS3_CR_EXC_CODE /* five bits */
+#undef MIPS1_CR_EXC_CODE
+#define MIPS1_CR_EXC_CODE R3900_CR_EXC_CODE
+
+/*
+ * [status register]
+ * R3900 don't have PE, CM, PZ, SwC and IsC.
+ */
+#define R3900_SR_NMI 0x00100000 /* r3k PE position */
+#undef MIPS1_PARITY_ERR
+#undef MIPS1_CACHE_MISS
+#undef MIPS1_PARITY_ZERO
+#undef MIPS1_SWAP_CACHES
+#undef MIPS1_ISOL_CACHES
+
+/*
+ * [context register]
+ * - no changes.
+ */
+
+
+/*
+ * TX3900 Coprocessor 0 registers
+ */
+#define R3900_COP_0_CONFIG $3
+#define R3900_COP_0_DEBUG $16
+#define R3900_COP_0_DEPC $17
+
+#define R3920_COP_0_PAGEMASK $5
+#define R3920_COP_0_WIRED $6
+#define R3920_COP_0_CACHE $7
+#define R3920_COP_0_TAG_LO $20
+
+/*
+ * TLB entry
+ * 3912 ... TLB entry is 64bits wide and R3000A compatible
+ * 3922 ... TLB entry is 96bits wide
+ */
+
+/*
+ * Index register
+ * 3912 ... index field[8:12] (32 entry)
+ */
+#define R3900_TLB_NUM_TLB_ENTRIES 32
+#define R3920_TLB_NUM_TLB_ENTRIES 64
+#undef MIPS1_TLB_NUM_TLB_ENTRIES
+#ifdef TX391X
+#define MIPS1_TLB_NUM_TLB_ENTRIES R3900_TLB_NUM_TLB_ENTRIES
+#elif defined TX392X
+#define MIPS1_TLB_NUM_TLB_ENTRIES R3920_TLB_NUM_TLB_ENTRIES
+#endif
+
+/*
+ * Config register (R3900 specific)
+ */
+#define R3900_CONFIG_ICS_SHIFT 19
+#define R3900_CONFIG_ICS_MASK 0x00380000
+#define R3900_CONFIG_ICS_1KB 0x00000000
+#define R3900_CONFIG_ICS_2KB 0x00080000
+#define R3900_CONFIG_ICS_4KB 0x00100000
+#define R3900_CONFIG_ICS_8KB 0x00180000
+#define R3900_CONFIG_ICS_16KB 0x00200000
+
+#define R3900_CONFIG_DCS_SHIFT 16
+#define R3900_CONFIG_DCS_1KB 0x00000000
+#define R3900_CONFIG_DCS_2KB 0x00010000
+#define R3900_CONFIG_DCS_4KB 0x00020000
+#define R3900_CONFIG_DCS_8KB 0x00030000
+#define R3900_CONFIG_DCS_16KB 0x00040000
+
+
+#define R3900_CONFIG_DCS_MASK 0x00070000
+#define R3900_CONFIG_CWFON 0x00004000
+#define R3900_CONFIG_WBON 0x00002000
+#define R3900_CONFIG_RF_SHIFT 10
+#define R3900_CONFIG_RF_MASK 0x00000c00
+#define R3900_CONFIG_DOZE 0x00000200
+#define R3900_CONFIG_HALT 0x00000100
+#define R3900_CONFIG_LOCK 0x00000080
+#define R3900_CONFIG_ICE 0x00000020
+#define R3900_CONFIG_DCE 0x00000010
+#define R3900_CONFIG_IRSIZE_SHIFT 2
+#define R3900_CONFIG_IRSIZE_MASK 0x0000000c
+#define R3900_CONFIG_DRSIZE_SHIFT 0
+#define R3900_CONFIG_DRSIZE_MASK 0x00000003
+
+/*
+ * R3900 CACHE instruction (not MIPS3 cache op)
+ */
+#define R3900_MIN_CACHE_SIZE 1024
+#define R3900_MAX_DCACHE_SIZE (8 * 1024)
+#ifndef OP_CACHE
+#define OP_CACHE 057
+#endif
+#define R3900_CACHE(op, offset, base) \
+ .word (OP_CACHE << 26 | ((base) << 21) | ((op) << 16) | \
+ ((offset) & 0xffff))
+#define R3900_CACHE_I_INDEXINVALIDATE 0
+#define R3900_CACHE_D_HITINVALIDATE 0x11
+
+#define A0 4
+#define A3 7
+#define T0 8
+
+
diff -x CVS -urN mips.orig/include/vmparam.h mips/include/vmparam.h
--- mips.orig/include/vmparam.h Sat Apr 24 17:10:38 1999
+++ mips/include/vmparam.h Sat Oct 30 22:46:16 1999
@@ -134,7 +134,11 @@
#define VM_MAXUSER_ADDRESS ((vaddr_t)0x80000000)
#define VM_MAX_ADDRESS ((vaddr_t)0x80000000)
#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)0xC0000000)
+#ifdef ENABLE_MIPS_TX3900
+#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)0xFF000000)
+#else
#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)0xFFFFC000)
+#endif
/* virtual sizes (bytes) for various kernel submaps */
#define VM_KMEM_SIZE (NKMEMCLUSTERS*CLBYTES)
diff -x CVS -urN mips.orig/mips/db_interface.c mips/mips/db_interface.c
--- mips.orig/mips/db_interface.c Thu Oct 28 15:54:16 1999
+++ mips/mips/db_interface.c Sat Oct 30 22:46:16 1999
@@ -284,7 +284,7 @@
int i;
extern void mips1_TLBRead __P((int, struct mips1_tlb *));
- for (i = 0; i < MIPS1_TLB_NUM_TLB_ENTRIES; i++) {
+ for (i = 0; i < mips_num_tlb_entries; i++) {
mips1_TLBRead(i, &tlb);
db_printf("TLB%c%2d Hi 0x%08x Lo 0x%08x",
(tlb.tlb_lo & MIPS1_PG_V) ? ' ' : '*',
diff -x CVS -urN mips.orig/mips/locore.S mips/mips/locore.S
--- mips.orig/mips/locore.S Thu Nov 18 15:47:49 1999
+++ mips/mips/locore.S Sun Nov 21 02:49:26 1999
@@ -99,6 +99,16 @@
#ifdef __GP_SUPPORT__
la gp, _C_LABEL(_gp)
#endif
+
+#ifdef R3900_CACHE_DISABLE
+ li t0, ~(R3900_CONFIG_ICE|R3900_CONFIG_DCE)
+ mfc0 t1, R3900_COP_0_CONFIG
+ and t1, t0, t1
+ nop
+ mtc0 t1, R3900_COP_0_CONFIG
+ nop
+#endif /* R3900_CACHE_DISABLE */
+
#ifdef SOFTFLOAT /* No FPU; avoid touching FPU registers */
li t0, 0 # Disable interrupts and
mtc0 t0, MIPS_COP_0_STATUS # the fp coprocessor
diff -x CVS -urN mips.orig/mips/locore_mips1.S mips/mips/locore_mips1.S
--- mips.orig/mips/locore_mips1.S Wed Nov 10 17:06:11 1999
+++ mips/mips/locore_mips1.S Sun Nov 21 18:35:34 1999
@@ -1204,7 +1204,7 @@
*
*----------------------------------------------------------------------------
*/
-
+#ifndef ENABLE_MIPS_TX3900
/*----------------------------------------------------------------------------
*
@@ -1536,7 +1536,160 @@
j ra
nop
END(mips1_wbflush)
+#else /* !ENABLE_MIPS_TX3900 */
+/*
+ * Cache code for R3900
+ */
+/*
+ * void mips1_ConfigCache(void)
+ */
+LEAF(mips1_ConfigCache)
+ mfc0 t0, R3900_COP_0_CONFIG
+ li t1, R3900_CONFIG_ICS_MASK
+ and t1, t1, t0
+ srl t1, t1, R3900_CONFIG_ICS_SHIFT
+ li t2, R3900_MIN_CACHE_SIZE
+ sllv t1, t2, t1
+ sw t1, _C_LABEL(mips_L1ICacheSize)
+
+ li t1, R3900_CONFIG_DCS_MASK
+ and t1, t1, t0
+ srl t1, t1, R3900_CONFIG_DCS_SHIFT
+ li t2, R3900_MIN_CACHE_SIZE
+ sllv t1, t2, t1
+ sw t1, _C_LABEL(mips_L1DCacheSize)
+
+ j ra
+ nop
+END(mips1_ConfigCache)
+/*
+ * R3900 2-way set-associative, line size 4byte(3900)/16byte(3920)
+ * void mips1_FlushDCache(vaddr_t addr, vsize_t len)
+ */
+LEAF(mips1_FlushDCache)
+ lw t0, mips_L1DCacheLSize
+ addu a1, a1, a0 # compute ending address
+1:
+ R3900_CACHE(R3900_CACHE_D_HITINVALIDATE, 0, A0)
+ addu a0, a0, t0
+ bne a0, a1, 1b
+ nop
+
+ j ra
+ nop
+END(mips1_FlushDCache)
+
+/*
+ * R3900 direct-mapped/2-way set-associative line size 16byte
+ * void mips1_FlushICache(vaddr_t addr, vsize_t len)
+ */
+LEAF(mips1_FlushICache)
+ mfc0 t0, MIPS_COP_0_STATUS # Save SR
+ nop
+ mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
+ nop
+ # Disable I-cache
+ li t1, ~R3900_CONFIG_ICE
+ mfc0 t2, R3900_COP_0_CONFIG
+ and t1, t1, t2
+ nop
+ mtc0 t1, R3900_COP_0_CONFIG
+ j 2f # stop streaming
+ nop
+2:
+ # Flush I-cache
+ addu a1, 127
+ srl a1, a1, 7 # Number of unrolled loops
+3:
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 0, A0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 16, A0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 32, A0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 48, A0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 64, A0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 80, A0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 96, A0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 112, A0)
+ addu a1, -1
+ bne a1, zero, 3b
+ addu a0, 128
+
+ # Enable I-cache
+ nop
+ mtc0 t2, R3900_COP_0_CONFIG
+ nop
+ mtc0 t0, MIPS_COP_0_STATUS # enable interrupts
+ j ra # return and run cached
+ nop
+END(mips1_FlushICache)
+
+/*
+ *
+ * void mips_FlushCache(void)
+ */
+LEAF(mips1_FlushCache)
+ lw t1, mips_L1ICacheSize
+ lw t2, mips_L1DCacheSize
+# lw t3, mips_L1ICacheLSize
+# lw t4, mips_L1DCacheLSize
+ nop
+ mfc0 t7, MIPS_COP_0_STATUS # Save SR
+ nop
+ mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts.
+ nop
+ # Disable I-cache
+ li t5, ~R3900_CONFIG_ICE
+ mfc0 t6, R3900_COP_0_CONFIG
+ and t5, t5, t6
+ nop
+ mtc0 t5, R3900_COP_0_CONFIG
+ j 2f # stop streaming
+ nop
+2:
+ # Flush cache
+ li t0, MIPS_KSEG0_START
+ addu t1, t0, t1 # End address
+ subu t1, t1, 128
+3:
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 0, T0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 16, T0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 32, T0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 48, T0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 64, T0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 80, T0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 96, T0)
+ R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 112, T0)
+ bne t0, t1, 3b
+ addu t0, t0, 128
+
+ # Flush D-cache
+ la t0, dummy_buffer
+ addu t1, t0, t2 # End address
+4:
+ lw t2, 0(t0)
+ bne t1, t0, 4b
+ addiu t0, t0, 4
+
+ # Enable I-cache
+ nop
+ mtc0 t6, R3900_COP_0_CONFIG
+ nop
+ mtc0 t7, MIPS_COP_0_STATUS # enable interrupts
+ j ra # return and run cached
+ nop
+END(mips1_FlushCache)
+
+LEAF(mips1_wbflush)
+ nop
+ sync
+ nop
+ j ra
+ nop
+END(mips1_wbflush)
+
+ .comm dummy_buffer, R3900_MAX_DCACHE_SIZE
+
+#endif /* !ENABLE_MIPS_TX3900 */
/*
* mips1_proc_trampoline
*
diff -x CVS -urN mips.orig/mips/mips_machdep.c mips/mips/mips_machdep.c
--- mips.orig/mips/mips_machdep.c Thu Nov 18 15:47:49 1999
+++ mips/mips/mips_machdep.c Sun Nov 21 02:49:36 1999
@@ -131,6 +131,9 @@
#endif
#ifdef MIPS1
+#ifdef ENABLE_MIPS_TX3900
+int r3900_icache_direct;
+#endif
/*
* MIPS-I (r2000 and r3000) locore-function vector.
*/
@@ -356,6 +359,27 @@
cpu_arch = 1;
mips_num_tlb_entries = MIPS1_TLB_NUM_TLB_ENTRIES;
break;
+#ifdef ENABLE_MIPS_TX3900
+ case MIPS_TX3900:
+ cpu_arch = 1;
+ switch (cpu_id.cpu.cp_majrev) {
+ default:
+ panic("not supported revision");
+ case 1: /* TX3912 */
+ mips_num_tlb_entries = 32;
+ r3900_icache_direct = 1;
+ mips_L1ICacheLSize = 16;
+ mips_L1DCacheLSize = 4;
+ break;
+ case 3: /* TX3922 */
+ mips_num_tlb_entries = 64;
+ r3900_icache_direct = 0;
+ mips_L1ICacheLSize = 16;
+ mips_L1DCacheLSize = 16;
+ break;
+ }
+ break;
+#endif /* ENABLE_MIPS_TX3900 */
#endif /* MIPS1 */
#ifdef MIPS3
@@ -462,7 +486,11 @@
{ MIPS_R8000, "MIPS R8000 Blackbird/TFP CPU", 4 },
{ MIPS_R4600, "QED R4600 Orion CPU", 3 },
{ MIPS_R4700, "QED R4700 Orion CPU", 3 },
+#ifdef ENABLE_MIPS_TX3900
+ { MIPS_TX3900, "Toshiba TX3900 CPU", 1 }, /* see below */
+#else
{ MIPS_TX3900, "Toshiba TX3900 or QED R4650 CPU", 1 }, /* see below */
+#endif
{ MIPS_R5000, "MIPS R5000 CPU", 4 },
{ MIPS_RC32364, "IDT RC32364 CPU", 3 },
{ MIPS_RM5230, "QED RM5200 CPU", 4 },
@@ -539,8 +567,16 @@
printf("cpu0: ");
#ifdef MIPS1
if (cpu_arch == 1) {
+#ifdef ENABLE_MIPS_TX3900
+ printf("%dKB/%dB Instruction %s, %dKB/%dB Data 2-way set associative, %d TLB entries",
+ mips_L1ICacheSize / 1024, mips_L1ICacheLSize,
+ r3900_icache_direct ? "direct mapped" : "2-way set associative",
+ mips_L1DCacheSize / 1024, mips_L1DCacheLSize,
+ mips_num_tlb_entries);
+#else /* ENABLE_MIPS_TX3900 */
printf("%dKB Instruction, %dKB Data, direct mapped cache",
mips_L1ICacheSize / 1024, mips_L1DCacheSize / 1024);
+#endif /* ENABLE_MIPS_TX3900 */
}
#endif
#ifdef MIPS3
diff -x CVS -urN mips.orig/mips/pmap.c mips/mips/pmap.c
--- mips.orig/mips/pmap.c Sun Nov 14 08:16:39 1999
+++ mips/mips/pmap.c Sun Nov 21 02:53:31 1999
@@ -267,6 +267,9 @@
#ifdef SYSVSHM
Sysmapsize += shminfo.shmall;
#endif
+#ifdef KSEG2IOBUFSIZE
+ Sysmapsize += (KSEG2IOBUFSIZE >> PGSHIFT);
+#endif
Sysmap = (pt_entry_t *)
pmap_steal_memory(sizeof(pt_entry_t) * Sysmapsize, NULL, NULL);
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