Subject: VM implementation peculiar to MIPS processor
To: None <port-mips@netbsd.org>
From: Toru Nishimura <nisimura@itc.aist-nara.ac.jp>
List: port-mips
Date: 05/27/1999 12:24:22 
Two things of MIPS VM implementation.

1. R3000 processor can handle 'no cache' attribute on pages on the fly
   having such TLB entries marked so.  R4000 provides more control over it.
   How can we utilize the functionalities given NetBSD UVM framework?

2. If pmap_copy_page()/pmap_zero_page() had VA rather than PA, what the
   impact would involve?	 

Tohru Nishimura