[ R4000 NetBSD/mips is suffered from cache oddness ]

>> I committed all our changes which were machine independent.  That's 
>> why I'm confused. The last pmap.c which I've synched to is 1.50.
>> 
>> The relevant changes are those related to mips_flushcache_allpvh.
>
> Mmm, unfortunately, that version doesn't fix our problem.
>
> Both the kluge which disables cache entirely, or the kluge which
> increases page size bigger than the primary cache size fixed the
> problem. So I suspect this is virtual alias problem of mips primary
> cache, and not fixed cleanly, yet.

pmap.new.c for NetBSD/mips is under development.  It should be
mips64-ready to provide 1TB user space. (Hi, Jason)

BTW, I've finally noticed 'Advanced RISC Computing Specification 1.2'
refers to the requirement of 'cross-processor interrupt' for SMP ARC
box, the existence of it made me happy implementing efficient TLB
shootdown algorithm with SMP kernel.  (I thought SMP NetBSD/mips was
far beyond the horizon.)  Does anyone out there have specific details
of how the 'cross-processor interrupt machinary' is implemented and
used with such the 'SMP Windows NT boxes' ???

Tohru Nishimura
Nara Institute of Science and Technology