>fixed.
>This was the bug of mips shared locore.S.
>I suppose that this bug also damages to the performance of R4000 pmax.

It depends if the interrupt for the on-chip cycle counter is enabled.
On pmaxes, it isn't, due to spl hackery.


>Then, the other problem appeared.
>This is the harder type problem. :-<
>(heap area is corrupted by erroneous code.)

[boot log] 

Amazing progress. Very very nice.

Does the machine have an L2 cache?

If not, did you define MIPS3_FLUSH? Does the problem go away if you
do?  The ``normal'' codepath relies on an L2 cache to warn about
aliases in the virtually-indexed L1 cache; if you dont have an L2
cache you can get nasty aliasing problems. Some ARC machines do, some
dont.

There's one other place (noted in a comment) where pefo's pica code
used to flush out the segmap pages.  I've always been slighlty
confused about why, and if there's a more efficient way to handle it.