Subject: Re: R4000 cache lines
To: Michael L. Hitch <>
From: Jonathan Stone <jonathan@DSG.Stanford.EDU>
List: port-mips
Date: 06/03/1998 15:22:38
>>   The only problem I see with Jason's change is the same problem I have with
>> some of the cache flushing in pmap:  it flushes all the entries within the
>> virtually-indexed range.  This could be flushing entries containing
>> different physical addresses/tags, which is not necessary.  I don't see
>> any easy way around that though.

>Yah, sigh.  But, what to do about flushing for user space addresses for
>non-curproc?  Grovel the pmap's software page tables and look into the
>cache registers?

Hm.  can the mips3 "cache" insn handle physical addresses?

If it did, you could grovel, and then selectively writeback or
invalidate the physical pages.  (Virtual addresses arent quite enough,
since they could miss in the TLB.)

That's what michael and I had talked about doing for the cachectl
operations needed for (amongst other things) gcc/g++'s onstack
trampoline code, way back when.