Subject: Re: R4000 cache lines
To: None <port-mips@NetBSD.ORG>
From: Michael L. Hitch <mhitch@lightning.oscs.montana.edu>
List: port-mips
Date: 06/03/1998 10:17:22
On Jun  3,  8:17am, Jason Thorpe wrote:
> Ok, then *crosses fingers* the changes I committed should DTRT, except
> for userspace addresses... don't know how to deal with those, per se,
> because the process that requested the I/O may not be the current process,
> and so a TLB miss would spell disaster.

  I was going to ask if there would ever be a userspace address.  I don't
know of any case where it might be - as far as I know, any I/O to userspace
is done through kernel virtual addresses.  The one case that will currently
cause problems on the mips is if the address is on the kernel stack.  The
kernel stack is still being mapped at UADDR, and the mapping may change
between process context switches.

  The only problem I see with Jason's change is the same problem I have with
some of the cache flushing in pmap:  it flushes all the entries within the
virtually-indexed range.  This could be flushing entries containing
different physical addresses/tags, which is not necessary.  I don't see
any easy way around that though.

Michael

-- 
Michael L. Hitch			mhitch@montana.edu
Computer Consultant
Information Technology Center
Montana State University	Bozeman, MT	USA