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Hello,

On Jan 31, 2007, at 20:27, Allen Briggs wrote:

> On Wed, Jan 31, 2007 at 08:20:40PM -0500, Michael Lorenz wrote:
>> Well, some other archs do the same, namely shark and prep, I'm pretty
>> sure there are more, so it's not that much of a curiosity.
>
> Well, it's a curiosity if you're expecting splhigh to block =
everything.

Since our docs say that splhigh blocks everything we should either=20
behave accordingly or change the docs.

>> Stupid question - why wouldn't we want DMA at least for sending?
>
> It might be OK, but for the console, I generally want things to be
> pretty much dead simple so that I know they'll work with all =
interrupts
> blocked for DDB or KGDB access.

We'd have to poll there anyway which means different handling which=20
would have to do without DMA. We could also use DMA only on speeds=20
higher than - say - 4000 interrupts per second. Or some margin based on=20=

CPU speed.

>> Z80 SIO programming some time before the previous ice age - if the =
mac
>> serials aren't too retarded compared to the Z80 SIO they should=20
>> support
>
> I don't recall what Z80 systems used for SIO.  The macs use either
> a real Z8530 or an ASIC core that should be bug-compatible.

Hmm, from the manual:
1.2 SCC=E2=80=99S CAPABILITIES The NMOS version of the SCC is Zilog=E2=80=99=
s original=20
device. The design is based on the Z80 SIO architecture. If you are=20
familiar with the Z80 SIO, the SCC can be treated as an SIO with=20
support circuitry such as DPLL, BRG, etc.

Ok, I retract that 'retarded' remark ;)

Ah well, I guess better look at the interrupt hierarchy, finish my ADB=20=

replacement drivers and so on before mucking with the serial ports.

have fun
Michael
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