On Sat, Jan 22, 2005 at 07:54:45AM -0500, Tim Kelly wrote:
> Now it'd be nice to figure out how a CPU that has an unrecognized
> version will get the CPU speed measured, as well as having an L2
> cache listed.

I think that new CPUs come out infrequently enough that this shouldn't
be an issue.  If someone's watching Motorola^WFreescale closely enough
to pick up new revisions of the docs when they come out, we can add
the info--otherwise, we add them when we see the chips in the wild
and go check the docs.

I think it would be a bit foolish to try and make assumptions about
new chips, which is what I think we'd have to do to deal with them
before they're documented.

Keep in mind that the powerpc/oea/cpu_subr.c, where most of this
code lies, can not depend on OFW.  (Otherwise, I think Apple has
put some clues in OFW for at least some things--like dfs.)

In any case, as I said earlier, I wouldn't worry too much about
it.  The failure mode is much less drastic than we have on ARM,
where we panic if the CPU is unrecognized...

-allen

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