Subject: Re: Interrupts and many slot machines
To: Nathan J. Williams <nathanw@wasabisystems.com>
From: Tim Kelly <hockey@dialectronics.com>
List: port-macppc
Date: 12/27/2004 14:14:34
At 10:11 PM -0500 12/11/04, Nathan J. Williams wrote:
>Tim Kelly <hockey@dialectronics.com> writes:
>>
>> That reminds me - I have a patch that will enable power saving mode on 604.
>> The CPU will support it, but doesn't have HID settings to go with it. It
>> just needs a variable set to true in cpu_subr.c. It cut my fan noise in
>> half, and after a day of idling the computer it seems just fine.
>
>Try some performance tests before and after. Power-saving modes often
>increase interrupt latency a great deal, with negative effects on
>things like disk and network performance.

Revisiting this issue, I have a question about identifying performance
bottlenecks. I can't quantitatively show the performance has decreased
since allowing the two 604 CPUs to be put into powersaving mode, but some
times it seems that perhaps performance is not ideal. Specifically, during
make depend on a kernel, I find that after hitting "swapbsd.c" the
compilation is slower than before. I have looked at top during the
compiling, and while the CPUs are both nearing 100% utilization, no process
exceeds more than 2 or 3% immediately following swapbsd.c. After passing
this point, processes will regularly hit 40 to 60% WCPU and half that CPU.

What compiling is after the swapbsd.c point, and what areas of the computer
would this affect? Allowing the CPUs to be put into MSR[POW] has had
positive results for myself and one other person, to the point that the (SP
or MP) -current kernel is not useable otherwise, so if this is harming
performance overall I'd like to examine what areas overall are affected.

thanks in advance,
tim