At 12:13 PM +0100 12/18/04, Riccardo Mottola wrote:

>Here are the bad news: the kernel doesn't get very far! right after CPU
>detection (which is detected correctly as a 604ev)
>
>I get
>
>cpu0: 350Mhztrap: pid 0.1 (swapper): kernel PGM trap @ 0x27ece8
>(SRR1=0x81032)
>panic: trap
>stopped in pid 0.1 (swapper) at netbsd cpu_Debugger+0x10   lwz r0, r1, 0
>
>now typing out the whoel bt is long but it says essentially:
>kernel PGM trap by cpu_config_l2cr
>ADBDevTable
>cpu_setup
>cpu_attach_common

With the change in CPU identification so that 604e and 604ev are properly
differentiated, this now allows probing of the backside L2 cache on the
604ev. This aspect is one of the tweaks I made to Allen's patch and was
committed. According to

http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs
-PPC_Desktop/PPC_Enhanced_8600_9600.pdf

the 604ev has 1MB of pipeline burst static RAM operating in write-through
mode on an "inline" L2 cache. However, according to

http://courses.cs.tamu.edu/cpsc462/walker/Appendices/dbug_book.pdf

which I found this morning, the L2CR register may not have been implemented
on this CPU. So my interpretation of "inline" as a "backside" cache is
mistaken. Documentation on the 604ev is sparse.

Apply

Index: cpu_subr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/powerpc/oea/cpu_subr.c,v
retrieving revision 1.16
diff -d -u -r1.16 cpu_subr.c
--- cpu_subr.c  8 Dec 2004 03:07:03 -0000       1.16
+++ cpu_subr.c  18 Dec 2004 12:13:01 -0000
@@ -448,8 +448,8 @@
                aprint_normal("%s: ", self->dv_xname);
                cpu_print_speed();

-               if (vers == MPC604ev || vers == MPC750 || vers == MPC7400 ||
-                   vers == IBM750FX || vers == MPC7410 || MPC745X_P(vers)) {
+               if (vers == MPC750 || vers == MPC7400 || vers == IBM750FX
+                        || vers == MPC7410 || MPC745X_P(vers)) {
                        if (MPC745X_P(vers)) {
                                cpu_config_l3cr(vers);
                        } else {

It removes 604ev from the CPUs that get their backside cache probed.

My apologies for the problem.

tim