At 7:53 AM -0500 12/6/04, Michael wrote:

>Figure out the cache's size and clock ratio, then add something like this
>to your kernel config ( and config, make depend, make... )
>options         L2CR_CONFIG="(L2SIZ_1M|L2CLK_20|L2RAM_PIPELINE_BURST)"
>This is what I did for my 300MHz G3 with 1MB cache at 150MHz, so clock
>ratio is 2, there are other macros for different sizes...


This is the big factor to know, the memory size. The G3 CPU will not accept
2M backside caches (the size value is actually defined as 0k for what is 2M
on G4).

>#define    L2SIZ_256K             0x10000000
>#define    L2SIZ_512K             0x20000000
>#define    L2SIZ_1M               0x30000000
>... ratios ...

There's only two speeds that are useful:

>#define    L2CLK_15               0x04000000 /*            / 1.5 */
>#define    L2CLK_20               0x08000000 /*            / 2   */

A lot of the aftermarket cards can do 1.5:1, but 2:1 is a sure bet to work.

>#define    L2RAM_FLOWTHRU_BURST   0x00000000
>#define    L2RAM_PIPELINE_BURST   0x01000000
>#define    L2RAM_PIPELINE_LATE    0x01800000

PIPELINE_LATE is generally for the second generation G4s with L3s.
FLOWTHRU_BURST is rarely used, as far as I can tell, and I believe included
for backwards compatibility. MPC750, IBM750FX, and MPC7400 are usually
happy with PIPELINE_BURST.

There is two other key attributes though:

#define L2CR_L2WT        0x00080000 /* 12: L2 write-through. */

If this bit is off, the method is write-back. write-through is conservative
and will always work, at the expense of some speed.

And

#define L2CR_L2OH         0x00030000 /* 14-15: L2 output hold. */
#defineL2CR_OH05          0x00000000/* 0.5 nS*/
#define L2CR_OH10         0x00010000/* 1.0 nS*/
#defineL2CR_OHLTE        0x00020000/* recommended late write hold */
#define L2CR_OHLNG       0x00030000/* longest output hold

This is how long the output from L2 is held for the CPU to read it. Go with
L2CR_OH10. OHLTE is for PIPELINE_LATE, and OH05 can be too fast.

tim