Hello,

> I didn't get the patch to apply as was posted, but that was unlikely to be
> because of the patch and more the cut and paste aspect.
Tried it - at least it didn't do anything bad for me :)

mainbus0 (root)
cpu0 at mainbus0: 750 (Revision 2.2), ID 0 (primary)
cpu0: HID0 8090c0a4<EMCP,DOZE,DPM,ICE,DCE,SGE,BTIC,BHT>
cpu0: 300.00 MHz, no-parity 1MB WB L2 cache (PB SRAM) at 2:1 ratio

Any chance to detect the L2 cache automatically? So far I always had to hard-code it into the kernel config.
( it's a phase5/NewerTech board, MacOS doesn't see the cache either without some extension to configure it, but then it works just fine with the mainboard cache as L3 )

have fun
Michael