Hello,

> I think there was a one line difference between the code the patch was
> diff'd against and what is in the tree now. All segments in the patch
> failed, but I saw nothing wrong with them other than being off by one line.
Hmm, my last cvs update was a bit more than a day ago...
Anyway, it applied just fine.

> Yes, I wrote some code to automatically size and enable L2 caches.
> 
> http://www.dialectronics.com/PowerPC/L2Config.c
Ok, I'll have a look :)

> I've been too busy with the other problems to work on the bootloader stuff
> for a while.
Me too - this interrupt problem gets on my nerves. Sure, I don't really need the audio board, but deadlocks like that should just not happen. Besides that, the MPEG video IO board sits in the same bus, thus sharing the same interrupt and would likely need an interrupt priority level higher than IPL_BIO too.

> I have also not decided if I want to go with adding pdisk
> support to the bootloader or to make sure MBR support is up to date in
> NetBSD/macppc. Old World Macs, which I do my testing on, appear to be quite
> comfortable with MBR and it would eliminate bootxx for these models if one
> didn't want to dual boot with MacOS on the same hard drive.
I have NetBSD alone on a drive and I wouldn't like an MSDOS partition just for the boot loader.

> Using MBR
> support instead gives me more options regarding testing bootloaders, as I
> feel that as much hardware as possible should be configured before the
> kernel sees it (somewhat like an extension to OF, which is what would
> normally enable L2 and L3 caches). 
Agreed, the ethernet portion of the E100 card would be another candidate ( OF doesn't see it for some reason ), but that would pretty
likely get too complex pretty soon.

> I also swap CPUs from time to time and
> I'd rather have the L2 configuring not hard coded into the kernel.
Sure. I only did it because it was the only way to get the L2 cache enabled at all.

have fun
Michael