Subject: Re: CVS commits for macppc
To: Michael <macallan18@earthlink.net>
From: Dave Huang <khym@azeotrope.org>
List: port-macppc
Date: 11/17/2004 14:32:13
On Wed, Nov 17, 2004 at 02:59:08PM -0500, Michael wrote:
> What kind of graphics board do you use? It may work these days if it's some ATi, if not then there's a patch to support at least 3Dfx and Matrox cards, probably others too but that hasn't been tested.

That info's all in the email I referenced, although I guess since the
log files got base64 encoded, it's a bit of a hassle to read :) It's
an ATI Radeon (as mentioned in the Subject line). Some details from
the XFree86.0.log file:

(--) PCI:*(0:16:0) ATI Radeon QD rev 0, Mem @ 0x98000000/27, 0x90080000/19, I/O@ 0x0400/8, BIOS @ 0x90000000/17
[ ... ]
(II) RADEON(0): vgaHWGetIOBase: hwp->IOBase is 0x03b0, hwp->PIOOffset is 0x0000
(II) RADEON(0): PCI bus 0 card 16 func 0
(**) RADEON(0): Depth 16, (--) framebuffer bpp 16
(II) RADEON(0): Pixel depth = 16 bits stored in 2 bytes (16 bpp pixmaps)
(==) RADEON(0): Default visual is TrueColor
(==) RADEON(0): RGB weight 565
(II) RADEON(0): Using 6 bits per RGB (8 bit DAC)
(--) RADEON(0): Chipset: "ATI Radeon QD (AGP)" (ChipID = 0x5144)
(--) RADEON(0): Linear framebuffer at 0x98000000
(--) RADEON(0): MMIO registers at 0x90080000
(--) RADEON(0): BIOS at 0x90000000
(--) RADEON(0): VideoRAM: 32768 kByte (64-bit DDR SDRAM)
(II) RADEON(0): initializing int10
(WW) RADEON(0): Unable to retrieve all of segment 0x0C0000.
(II) RADEON(0): No legacy BIOS found -- trying PCI
(EE) RADEON(0): Cannot read V_BIOS (5)
(WW) RADEON(0): Video BIOS not detected, using default PLL parameters!
(II) RADEON(0): PLL parameters: rf=2700 rd=67 min=12500 max=35000; xclk=16615
(==) RADEON(0): Using gamma correction (1.0, 1.0, 1.0)
(II) RADEON(0): Generic Monitor: Using hsync range of 27.00-82.00 kHz
(II) RADEON(0): Generic Monitor: Using vrefresh range of 50.00-72.00 Hz
(II) RADEON(0): Clock range:  12.50 to 350.00 MHz

Anyways, my best guess is that the sync signals are incorrect, but I
don't know why. I seem to recall someone posting a patch that changed
the PLL parameters, but that didn't work for me.