At 8:25 AM -0400 9/27/04, Tim Kelly wrote:
>>Sep 26 14:53:31 temp /netbsd: cpu0 at mainbus0: 7455 (Revision 2.1), ID 0
>>(prima
>>ry)
>>Sep 26 14:53:31 temp /netbsd: cpu0: HID0
>>8450c0bc<EMCP,TBEN,NAP,DPM,ICE,DCE,SGE,
>>BTIC,LRSTK,FOLD,BHT>
>>Sep 26 14:53:31 temp /netbsd: cpu0: 1000.00 MHz
>>Sep 26 14:53:31 temp /netbsd: cpu0: 256KB L2 cache, 2MB L3 backside cache
>
>Although I may not be of assistance, I am curious as to how these settings
>come to be. Have you added the L2/L3 setting to the kernel, or is Open
>Firmware doing the configuring?
>
>tim

Short (factual) answer: I have no idea.

Longer (but mostly speculative) answer:
I looked at this code a while back, and as I recall, the kernel has
a table of possible values for CPU type and some HW registers that it reads
to determine these things.  When I looked at the code (in the 1.5
timeframe) it "noticed" the L2 cache, and spit out a message, but
it didn't actually *enable* it.

-dgl-