on 2/25/03 1:00 AM, John Klos at john@ziaspace.com wrote:

> Hi,
> 
> I just got my new Sonnet 700 MHz G4 upgrade for my 9600. It's nice - it
> looks well built, runs very cool, and doesn't require special memory like
> the NewerTech accelerators did.
> 
> The chip is a 7455 with 256k of CPU speed L2 cache; the board has one meg
> of L3 cache running at 200 MHz (cpu/3.5).
> 
> So, next, I'd like to configure a kernel for this. On boot, it says:
> 
> cpu0 at mainbus0: 7450 (Revision 2.1), ID 0 (primary)
> cpu0: HID0 8450c0a4<EMCP,TBEN,NAP,DPM,ICE,DCE,SGE,BTIC,BHT>
> cpu0: 700.00 MHz
> cpu0: L2 cache not enabled
> 
> Then I added the following lines to my config file:
> options         L3CR_CONFIG="(L3CR_L3E)"
> options         L2CR_CONFIG="(L2CR_L2E)"
> 
> which gave me:
> 
> cpu0 at mainbus0: 7450 (Revision 2.1), ID 0 (primary)
> cpu0: HID0 8450c0a4<EMCP,TBEN,NAP,DPM,ICE,DCE,SGE,BTIC,BHT>
> cpu0: 700.00 MHz
> cpu0: 256KB L2 cache
> 
> Now, even though this board is significantly faster than the one it is
> replacing, I'd really love to use the L3 cache, too. However, reading
> spr.h implies that adding the option L3CR_L3SIZ should only be done for 2
> meg L3 cache sizes, so I left that out (L3 size (0=1MB, 1=2MB)).
> 
> So does anyone know how I might go about getting both the L2 and L3 cache
> to work at the same time? Also, where is the speed divisor set? I have a
> feeling I should be bugging Matt...

I don't have a short answer, but I also recently bought one of these cards
for my 7500, and I'd like to get it working.  I've already built a kernel
that enables the L2 cache, and looked into the L3 issue a bit.

I think we'll have to start by finding out what value the card needs in
L3CR, probably by booting into Mac OS and setting up the Sonnet software.
(There are some settings in there that appear to depend strongly on the
hardware design of the CPU card -- something about "clock sample points",
whatever that means -- so I don't think we can just make something up.)
I've tried this a couple of times with Mac OS 9, but the 9 utility I have
that dumps the L2CR (which I modified to try and dump L3CR) just crashes.  I
think the best bet will be to use XPostFacto to set up a Mac OS X
installation and install the Sonnet software for X.  (I should be able to do
this given a free evening or two.)  There are decent tools available that
can read L3CR on Mac OS X.

Once we figure out what the proper value is, we will need to add code to set
up L3CR.  According to the Motorola book on the 7450 family, this is
non-trivial, but the procedure they give doesn't look _too_ much more
complex than the existing code to set up L2CR (in
arch/powerpc/oea/cpu_subr.c).

It doesn't appear that anyone has added many of the field definitions in
L3CR to src/sys/arch/powerpc/include/spr.h.  The only ones there are the
bits for L3CR_L3E and L3CR_L3SIZ, whereas the book specifies most of the
bits in the register.  A little bit of time spent doing data entry should
solve this problem.

For anyone following along at home, the book I'm referencing (MPC7450UM) is
available as a PDF from the Motorola site here:

http://e-www.motorola.com/brdata/PDFDB/docs/MPC7450UM.pdf

The procedure for setting up the L3 cache is in section 3.7.3.1, and the
bitfields in L3CR are described in section 2.1.5.5.2.

-- monroe
------------------------------------------------------------------------
Monroe Williams                                         monroe@pobox.com