Hi,

I just got my new Sonnet 700 MHz G4 upgrade for my 9600. It's nice - it
looks well built, runs very cool, and doesn't require special memory like
the NewerTech accelerators did.

The chip is a 7455 with 256k of CPU speed L2 cache; the board has one meg
of L3 cache running at 200 MHz (cpu/3.5).

So, next, I'd like to configure a kernel for this. On boot, it says:

cpu0 at mainbus0: 7450 (Revision 2.1), ID 0 (primary)
cpu0: HID0 8450c0a4<EMCP,TBEN,NAP,DPM,ICE,DCE,SGE,BTIC,BHT>
cpu0: 700.00 MHz
cpu0: L2 cache not enabled

Then I added the following lines to my config file:
options         L3CR_CONFIG="(L3CR_L3E)"
options         L2CR_CONFIG="(L2CR_L2E)"

which gave me:

cpu0 at mainbus0: 7450 (Revision 2.1), ID 0 (primary)
cpu0: HID0 8450c0a4<EMCP,TBEN,NAP,DPM,ICE,DCE,SGE,BTIC,BHT>
cpu0: 700.00 MHz
cpu0: 256KB L2 cache

Now, even though this board is significantly faster than the one it is
replacing, I'd really love to use the L3 cache, too. However, reading
spr.h implies that adding the option L3CR_L3SIZ should only be done for 2
meg L3 cache sizes, so I left that out (L3 size (0=1MB, 1=2MB)).

So does anyone know how I might go about getting both the L2 and L3 cache
to work at the same time? Also, where is the speed divisor set? I have a
feeling I should be bugging Matt...

Thanks,
John Klos