On Thu, 21 Nov 2002, Jeff Walther wrote:

> >The first generation PowerMacs -- that is, the {6,7,8,9}1xx family -- have
> >lots of hardware in common with the PCI PowerMacs (and AV Quadras).  They
> >use MACE ethernet, 53C(F)94 SCSI, and CUDA adb.  They have an interrupt
> >controller that is similar to what is found on PCI PowerMacs.
> 
> Is there information on the PCI PowerMacs interrupt controller 
> available somewhere?   That's handled by the Grand Central chip, yes? 

Or later ones used Heathrow/Gatwick.  Yeah.


> I'm wondering how many interrupts there are, which are allocated 
> where, and what unused interrupts might be available.  In particular, 
> I'm wondering if there are unused interrupts run out to pins on the 
> Grand Central.

The answer to those questions are "it depends".  The interrupt assignment
varies from board to board.  The top level interrupt handling code gets
the mapping info from Open Firmware.  As for whether there are extra pins,
I have no idea.


> For example each slot in the six slot machines has it's own 
> interrupt.  The interrupt for each PCI slot is connected to its own 
> pin on Grand Central.  So three of those interrupts are not used in a 
> three slot machine, unless they are used by the built-in video 
> circuitry on the {7,8} {5,6} 00.

That is probably, but not definitely, correct.  It does assume that only
one grand central variant exists.  I don't know for certain whether that
is true or not.


Later,
David

---------------------------------------------------------------------
David A. Gatwood                                dgatwood@gatwood.net
Developer Docs Writer                             dgatwood@apple.com
Apple Computer                                  dgatwood@mklinux.org

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