It dies in cpu_config_l2cr() in sys/arch/powerpc/mpc6xx/cpu_subr.c, probably
right about here:

-----
                /* Disable interrupts and set the cache config bits. */
                msr = mfmsr();
                mtmsr(msr & ~PSL_EE);
#ifdef ALTIVEC
                asm volatile("dssall");
#endif
                asm volatile("sync");
-----

Since "dssall" is an AltiVec-only instruction, it seems likely that it's
causing the trap I see when I try to boot a kernel with 'options ALTIVEC' on
my G3 box.  Removing only that option and rebuilding allows me to boot.

I suspect that either the code should be more selective or this option
shouldn't be in GENERIC.  Is the 'cpu_altivec' variable already set up when
this code runs?

-- monroe
------------------------------------------------------------------------
Monroe Williams                                         monroe@pobox.com