On Sun, Jun 09, 2002 at 10:33:00AM +0900, Makoto Fujiwara wrote:
> bouyer> Should be fixed in pciide.c 1.156
> Thanks a lot, Manuel,
> 
> bouyer> 	bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
> bouyer> 	    IDEDMA_CMD + 0x1, 0x0b);
> Removing this line made no change.

OK

> 
> > wd0c: aborted command, interface CRC error reading fsbn 0 (wd0 bn 0; cn 0 tn 0 sn 0), retrying
> 
> bouyer> Hum, a CRC error could just be a cable problem. The 20268 doesn't have
> bouyer> explicit timings settings, it gets them by snooping the SET_FEATURE command.
> 
> I have run with 
> int wdcdebug_pciide_mask = 0x1f;
> and got following lines.
> ------------------------------
> Jun  9 08:45:56 harry /netbsd: root on wd1a dumps on wd1b
> Jun  9 08:45:56 harry /netbsd: root file system type: ffs
> Jun  9 08:45:50 harry savecore: no core dump
> Jun  9 08:46:13 harry /netbsd:   seg 0 len 512 addr 0x17a1000
> Jun  9 08:46:13 harry /netbsd: pciide_dma_start
> Jun  9 08:46:14 harry /netbsd: pciide_dma_finish: status 0x45
> Jun  9 08:46:14 harry /netbsd: wd0: transfer error, downgrading to Ultra-DMA mode 2
> Jun  9 08:46:14 harry /netbsd: wd0(pciide0:0:1): using PIO mode 4, Ultra-DMA mode 2 (Ultra/33) (using D
> MA data transfers)
> Jun  9 08:46:14 harry /netbsd: wd0c: aborted command, interface CRC error reading fsbn 0 (wd0 bn 0; cn 
> 0 tn 0 sn 0), retrying
> Jun  9 08:46:14 harry /netbsd:   seg 0 len 512 addr 0x17a1000
> Jun  9 08:46:14 harry /netbsd: pciide_dma_start
> Jun  9 08:46:14 harry /netbsd: pciide_dma_finish: status 0x44
> Jun  9 08:46:14 harry /netbsd: wd0: soft error (corrected)
> ------------------------------
> 0x45 on the above 6th line seems to say underrun, for we have
> the line in pciide.c:
> 
>  1207     if ((status & IDEDMA_CTL_ACT) != 0) {
>  1208             /* data underrun, may be a valid condition for ATAPI */
>  1209             error |= WDC_DMAST_UNDER;
> 
> Is there anything to adjust for DMA timing ?

No, not on this controller as far as I know. It snoops the command register
for SET_FEATURE commands sent to the drive(s) and adjust its timings
appropriately.
But I don't have the data sheet for this controller, so I can only rely
on what other said me.

-- 
Manuel Bouyer <bouyer@antioche.eu.org>
--