I was pleased to see the e-mail suggesting how to enable L2
cache, but there is apparently more to it.

I'm running a PowerCenter 132 with a Sonnett 300Mhz/512Kb G3 card.

I tried several variations of options to make the backside cache work:

>options	L2CR_CONFIG="(L2SIZ_512K|L2CLK_20)"

Because I didn't know what kind of L2RAM I had, and because I misread the code
at first, I tried this.  This did not enable the L2cache at all.
This is because the code explicitly checks for L2CR_L2E (cache enable)?

>options	L2CR_CONFIG="(L2CR_L2E|L2SIZ_512K|L2CLK_20)"

I tried this next, on the thought that it would enable the cache.  It did.

>CPU: 750 (Revision 202)
>total memory = 98304 KB
>avail memory = 85280 KB
>using 1254 buffers containing 5016 KB of memory
>mainbus0 (root)
>cpu0 at mainbus0: 512KB backside cache
>trap type 300 at ff808ee0
>Stopped in swapper atÃ3ÃÃÃ3Ã3Ã3Ãß3å3e 700 at 24b0
>After
(And that was it...)

Didn't boot, though.


>options	L2CR_CONFIG="(L2CR_L2E|L2SIZ_512K|L2CLK_20|L2RAM_PIPELINE_BURST)"

Last, I tried this.
That didn't boot either.  Same as the above.

There is obviously more to this than meets the eye.  Looks like
no L2 cache is a pretty good option just now. ;->

-dgl-



At 9:09 AM -0600 1/4/01, Tsubai Masanari wrote:
>>As long as we're on the subject of kernels, does anyone know the use
>>of L2CR_CONFIG in cpu.c for macppc?
>
>Add, for example,
>
>options	L2CR_CONFIG="(L2SIZ_512K|L2CLK_20|L2RAM_PIPELINE_BURST)"
>(512K L2 cache, L2 clock is 1/2 of cpu clock, pipeline burst SRAM)
>
>to your kernel config.
>
>Possible parameters are:
>
>#define  L2SIZ_256K		0x10000000
>#define  L2SIZ_512K		0x20000000
>#define  L2SIZ_1M		0x30000000
>
>#define  L2CLK_10		0x02000000 /* core clock / 1   */
>#define  L2CLK_15		0x04000000 /*            / 1.5 */
>#define  L2CLK_20		0x08000000 /*            / 2   */
>#define  L2CLK_25		0x0a000000 /*            / 2.5 */
>#define  L2CLK_30		0x0c000000 /*            / 3   */
>
>#define  L2RAM_FLOWTHRU_BURST	0x00000000
>#define  L2RAM_PIPELINE_BURST	0x01000000
>#define  L2RAM_PIPELINE_LATE	0x01800000