On Tue, 02 Jan 2001 14:36:39 -0500, Bill Sommerfeld
<sommerfeld@orchard.arlington.ma.us> sez:

>> Yes, good points, but, except for the soft interrupts, (clock, net,
>> and serial), I say again, what is all this deferred interrupt
>> falderal, anyway?
> 
> I know ~nothing about the macppc interrupt architecture, so the
> following is speculation..
 
Neither do I, but I'm trying to catch up.  I know M68 pretty well, and
beginning to have a fair working knowledge of MPC86xx ppc....

Apparently the Official ppc architecture says that all external
interrupts vector through one interrupt routine, and is silent on the
concept of interrupt level like there is for the 68k.  (The MPC86xx
ppc's _do_ have interrupt levels defined for them, but that is a
construct of the cpm interrupt controller, which is an add-on to the
ppc core.)  Whatever IPL we want to fashion for the ppc is either our
own construct, or influenced, or perhaps dictated, by whatever
interrupt controller (pci bridge chip, maybe?) we find on the
motherboard.

This, I expect, (and if I remember correctly), is also the case with
the i386.  I remember some sort of interrupt controller with 286's,
but don't remember too much about priorities. (I don't care very much
for the Intel stuff.)

But I don't know anything at all about interrupt controllers & PCI, or
whatever might be on the macppc.

> 
> I haven't looked at how macppc does things in any detail, but on many
> ports (including i386), splfoo()/splx() doesn't actually touch the
> interrupt controller.  Instead, a regular global variable is used.
> 
> When a hardware interrupt occurs, the handler checks the software
> mask, and, if the interrupt is masked, it sets a bit in ipending and
> returns (otherwise, it handles the interrupt immediately).

We chose to do it this way because, perhaps, the hardware doesn't
prioritize interrupts, or automatically mask interrupts running on the
same or lower levels?  Or perhaps there are several different
interrupt controllers, and it's easier to do this generally in
software?

I'm wondering if this is the best scheme for macppc, or whether there
is a hardware model to follow.  My interest is the MPC86xx
controllers, which, as I said, have a defined interrupt priority
scheme.  I hope that there would be a substantial cross-over between
the two.

> splx()/spllower() checks ipending and calls a function
> (do_pending_int, in this case) if any bits are nonzero.
> 
> However, the macppc do_pending_int does run the handlers at splhigh()
> which eliminates many of the benefits of this scheme.
> 
>                                         - Bill

Yes, running the handlers at splhigh() seemed a bit screwy to me.  And
a good way to set these pending bits that gave us our current problem
in the first place.  Seems to me we can do better.

Anyway, thanks for your input, and much obliged for any further
insights.

-Mike