Arvid Bj=F6rkstr=F6m writes:
 > Now I've installed NetBSD onto my internal ide disk and I'm trying t=
o=20
 > boot but it just doesn't work.=20

I have had the same issue.

 > As I said earlier, it didn't find my external (Mac bootable) Ultra S=
CSI=20
 > disk and wanted to=20
 > install on my internal ide disk(wich I was running Mac OS on).
 > Is there a way to work around this problem or do I have to install N=
etBSD=20
 > onto my internal disk and then install it on my external disk once I=
 get=20
 > it up and running?

I have an 8500 with a G3 card and have had problems getting OF to boot
off of certain drives -- internal or external.

This is why something like BootX would be helpful.

I ended up buying a cheap,slow $15 300 MB SCSI disk just to get
started booting. I pass in the -a option and then tell it my "real"
root filesystem.

Some of my SCSI disks OF doesn't like, some NetBSD.

For others with G3 cards on pre-G3 PCI macs, I cobbled the following
together to start my backside cache. Note that I have hardcoded my
backside cache settings and that if the G3 cache is already enabled
some more logic must be added to flush and turn off the cache.

This is (obviously) not for general use, but might serve as on OK
starting point.

I someone else already working on this?

Added to arch/macppc/macppc/cpu.c:

/* called from cpuattach() */
static void rmore_init()
{
=09u_int l2cr;

=09__asm __volatile ("mfspr %0, 1017" : "=3Dr"(l2cr));

=09/*invadate the global */
=09l2cr |=3D L2CR_L2I;
=09
=09__asm __volatile ("mtspr 1017,%0" :: "r"(l2cr));

=09/*loop during the invalidate (waiting) */
=09do {
=09  __asm __volatile ("mfspr %0, 1017" : "=3Dr"(l2cr));
=09} while (l2cr & L2CR_L2IP);

=09/* turn invaldate off */
=09l2cr &=3D ~L2CR_L2I;

=09__asm __volatile ("mtspr 1017,%0" :: "r"(l2cr));
=09
=09/* enable the cache to the target settings */
=09l2cr =3D 0xAB000000;

=09__asm __volatile ("mtspr 1017,%0" :: "r"(l2cr));
}

The 0xAB000000 I got from the PowerLogic G3 Control Panel.

We should probably look into how BootX/LinixPCC pass in the backside
cache speed and try to use a similar mechanism.

Thanks,

-- Rod Morehead                    =20
   rmore@rmore.net
   http://rmore.net