Subject: Re: PowerLogix G3 Upgrade
To: Donald Lee <donlee_ppc@icompute.com>
From: Henry B. Hotz <hotz@jpl.nasa.gov>
List: port-macppc
Date: 11/11/1999 10:14:13
At 9:42 PM -0800 11/10/99, Donald Lee wrote:
>>On Tue, Nov 9, 1999, Henry B. Hotz <hotz@jpl.nasa.gov> wrote:
>>>Reading through the manual for the beast I find a statement that there is a
>>>"speculative read" capability for the cache which should be disabled on
>>>machines which did not originally have a G3 processor.  I take this to be a
>>>cache-coherency issue for motherboards which did not take this into
>>>account.
>>>
>>>Does the NetBSD kernel configure the G3 L2 cache with this (presumed)
>>>compatibility problem in mind?  Does anyone know the PowerPC chips well
>>>enough to comment?
>>
>>I don't think this has anything to do with cache coherency (but there are
>>some known coherency issues with some Apple chipsets, that's another
>>matter and is not related to the G3). I beleive the main reason here is
>>that the ROM (and some MacOS drivers) lack the necessary setting of the
>>guard bit and eieio() instructions to make sure HW accesses are properly
>>serialized on those machines. One known breaker is the Adaptec driver.
>
>It's not so much the driver as it is a combination of the
>way the Adaptec hardware expects mem access to work and
>the lack of the guard bit.  The pre-G3 mac ROMs didn't envision the
>future aggressive optimizations in the G3, so they couldn't "guard"
>against them properly. (sorry ;-> )
>
>The driver is "correct" for accesses that have the guard bit set correctly.
>(The appropriate eieio() instructions are present)
>There is actually not much that can be done just with SW that is not pretty
>brutal if the guard bit is not set properly on the HW ranges.

So if I wanted to put my Adaptec 2940UW in the machine I would have a
problem.  Is there any standard Apple hardware which is a problem?  Is
there a list somewhere of known problems?

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