On Tue, Nov 9, 1999, Henry B. Hotz <hotz@jpl.nasa.gov> wrote:

>I just put the above-mentioned G3 upgrade into my 8500.  All of $169 at
>Other World Computing.  Nice, though it doesn't speed up web surfing over a
>modem much.
>
>Reading through the manual for the beast I find a statement that there is a
>"speculative read" capability for the cache which should be disabled on
>machines which did not originally have a G3 processor.  I take this to be a
>cache-coherency issue for motherboards which did not take this into
>account.
>
>Does the NetBSD kernel configure the G3 L2 cache with this (presumed)
>compatibility problem in mind?  Does anyone know the PowerPC chips well
>enough to comment?

I don't think this has anything to do with cache coherency (but there are
some known coherency issues with some Apple chipsets, that's another
matter and is not related to the G3). I beleive the main reason here is
that the ROM (and some MacOS drivers) lack the necessary setting of the
guard bit and eieio() instructions to make sure HW accesses are properly
serialized on those machines. One known breaker is the Adaptec driver.

I beleive that once you are in the netbsd kernel, if your CPU is detected
as a G3, the kernel will do whatever is needed to guard the io ranges, so
you should not need to worry about this.