At 6:22 PM -0500 11/20/02, Michael R. Zucca wrote:
>David Gatwood wrote:
>
>>The big advantage to this scheme is that, with the exception of the few
>>milliseconds needed to increment a simple counter, interrupts are never
>>disabled, which means interrupts never get lost, although clock interrupts
>>can get queued up for a while in the worst case.  The only significant
>>disadvantage is that there might be a slight drop in i/o performance,
>>since most I/O would now be handled in a thread (albeit a high priority
>>kernel thread).
>
>Well, there are a few points:
>1. Make this an option so that machines like the Quadras where we 
>can put the clock interrupt at a better level aren't forced to take 
>the I/O performance hit for this fix.

Do we actually support the alternate interrupt scheme yet?  I know 
someone was working on it once. . .
-- 
The opinions expressed in this message are mine,
not those of Caltech, JPL, NASA, or the US Government.
Henry.B.Hotz@jpl.nasa.gov, or hbhotz@oxy.edu