On Mon, 3 Jun 2002, David A. Gatwood wrote:

> On Mon, 3 Jun 2002, Nyef wrote:
>
> > > 1.  The two modes of SWIM are IWM and ISM, not IWM and SWIM.
> >
> > Okay. I just called it SWIM mode because it was new to the SWIM chip and
> > none of the documentation I could find even _mentioned_ a mode switch.
>
> Heh.  Well, the chip isn't exactly documented....

My point exactly. ^_-

What, exactly, does SWIM _really_ stand for, anyway? A quick search with
Google turns up at least three different possibilities...

> > > 2.  Yes, HDSEL can be set in either place.  You should probably control it
> > > on the chip where possible, despite what classic Mac OS does.
> >
> > Huh. I'd have thought that it would depend on the way the hardware is set
> > up. Is this a wired-OR setup?
>
> Not sure.  Don't have a wiring diagram.  (Well, I probably do, but I don't
> care that much. ;-)  To be safe, set it in both places.

I'll check to see if the chip-only version works on my IIcx once I get it
working again (-if- I get it working again)... Gonna try replacing the
internal battery tomorrow...

> You should really do GCR in ISM mode, BTW, not in IWM mode.  It saves the
> overhead and general clumsiness of doing a mode switch while probing a
> newly-inserted disk.  Also, you'll have to do it in ISM mode when you try
> to add support for the SWIM II.  Might as well get it over with.

My first instinct is to say no here. No sense in breaking already-working
GCR support even if it does use IWM mode. And there is as yet no evidence
that the SWIM I chips even support GCR over ISM. On the other paw, finding
out for certain could be useful... Again, once I get my IIcx working...

> The SWIM III code documents how to turn off the trans-space machine (MFM
> encoder)  and how to do the GCR decoding and encoding in software.  The
> only thing you'll have to figure out is how to set up the cell clock, and
> you pretty much have to figure that out anyway, I think.

Let me guess. This is something in parameter memory that depends on the
current disk tach reading? (I have vague memories of seeing something like
this in one of the disassemblies I did a while back)

> > I was thinking that the read/write select was dependant on that address
> > bit for the SWIM I.
>
> Don't know.  I thought you could treat it just like the bottom half of a
> SWIM III, but I may be completely wrong.  If the 9 code treats them
> differently, then trust the 9 code and ignore me.  :-)

Umm... "9 code"?

---------------------------
All programming can be viewed as an exercise.
---------------------------
Alastair Bridgewater
e-mail: nyef@softhome.net