At 8:44 Uhr -0400 10.4.2002, Michael R. Zucca wrote:
>At 3:25 PM -0400 4/9/02, Hauke Fath wrote:
>
>>Which leads to the question: How do we support 2nd level caches (IIci,
>>IIfx, accelerator boards, 840AV, the AWS95 cache, the Daystar cache cards,
>>...) when we get bus_dma?
>
>Well, that's "easy" :-) If we can put together flush/invalidate code for
>those caches, we'll have to integrate it into bus_dma. Maybe we should have
>something in locore or something that provides different flush/invalidate
>asm routines for bus_dma depending on the model type.

[...]
mainbus0 (root)
memcache0 at mainbus0: 32 KByte, write-through
[...]

?
	hauke


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