At 3:25 PM -0400 4/9/02, Hauke Fath wrote:

>Which leads to the question: How do we support 2nd level caches (IIci,
>IIfx, accelerator boards, 840AV, the AWS95 cache, the Daystar cache cards,
>...) when we get bus_dma?

Well, that's "easy" :-) If we can put together flush/invalidate code for
those caches, we'll have to integrate it into bus_dma. Maybe we should have
something in locore or something that provides different flush/invalidate
asm routines for bus_dma depending on the model type.

>Fortunately, Allen has picked up the ball, so we may see an MI
>implementation soon. As I said, the differences between the m68k ports'
>bus_dma ways are not that great, it's just that x68k has re-structured a
>few things.

Still, I'll probably still grab the x68k bus_dma in the mean time since you
have shown it to be working. That way I can get some work done while Allen
tries to eek out NetBSD time. :-)

>I integrated the x68k _dmamap_sync() and its helper functions, and after I
>removed a previous low-level attempt at flushing the cache (pulled from
>amiga, iirc) -- voil=E0! -- I finally got identical output from 53c720
>accesses to main memory as to its board RAM. Meaning, the thing actually
>does DMA via NuBus, and gets its scripts allright. Success!

Awesome!

Sounds like good progress is being made around here lately!


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 Michael Zucca - mrz5149@acm.org
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