Subject: Re: QuadraLink serial port card
To: David A. Gatwood <dgatwood@mvista.com>
From: Bill Studenmund <wrstuden@nas.nasa.gov>
List: port-mac68k
Date: 07/22/1999 12:31:43
On Thu, 22 Jul 1999, David A. Gatwood wrote:

> On Thu, 22 Jul 1999, Bill Studenmund wrote:
> 
> > On Wed, 21 Jul 1999, David A. Gatwood wrote:
> > 
> > > Oh, I understand.  You mean if the IOP could be controlled through DMA.  I
> > > was suggesting that, by that description, the IOP acts like a DMA engine,
> > > in that it reads from a section of memory and dumps it out in time through
> > > the port.  The buffer that it reads from being fixed reminds me of the
> > > AMIC DMA used in the x100 PowerMacs.  Same sort of issues, I assume.

> It's the DMA engine used to drive all of the above -- SCSI, ethernet,
> floppy, and serial... I think that's it.

Given that answer, by my understanding of the IOP's, they're different.
From what I've gleaned from talking to developers (admittendly like 5
years ago) was that the CPU is responsable for reading transmit data from
main memory, and writing receive data to main memory.

The reason this isn't bad is that the copy can happen all at once, so the
CPU only has to serice one interrupt for the whole lot. :-) It's not as
nice as DMA as the CPU has to be involved. :-(

Take care,

Bill