On Wed, 21 Jul 1999, Bill Studenmund wrote:

> As I understand it (which might be wrong), it's like there is either a
> FIFO or a shared memory space (like an Ehternet card's memory) into which
> the CPU copies the data, from which the IOP reads it.
> 
> If it were DMA, the CPU'd just pass the IOP the in-host-memory address of
> the data and go from there. There'd be no CPU_copying step. :-)

Oh, I understand.  You mean if the IOP could be controlled through DMA.  I
was suggesting that, by that description, the IOP acts like a DMA engine,
in that it reads from a section of memory and dumps it out in time through
the port.  The buffer that it reads from being fixed reminds me of the
AMIC DMA used in the x100 PowerMacs.  Same sort of issues, I assume.


David