This note is cross-posted on both Postgres-hackers and port-mac68k/NetBSD
in order to get a more complete discussion.

At 3:42 PM -0700 5/26/99, Bill Studenmund wrote:
>On Wed, 26 May 1999, Bill Studenmund wrote:
>
>> On Wed, 26 May 1999, Henry B. Hotz wrote:
>>
>> > At 12:16 PM -0700 5/26/99, Bill Studenmund wrote:
>> > >Does the TAS instruction need hardware support?
>> >
>> > Well, sort-of.  It needs a 68000 family CPU. ;-)
>>
>> What I meant was, I thought that the TAS instruction generated a special
>> read-modify-write istruction. If so, does the mac68k hardware support it?
>
>More specifically, does the Apple memory system support the special memory
>cycle used by the TAS instruction?
>
Ah! That's a good question.  I don't know.  Anyone else?

In the case of Postgres it may not matter because I believe the routine in
question is only used to coordinate multiple DBMS backend tasks.  This
means we only need things atomic at the interrupt level, not at the memory
access level.

Can anyone on pg-hackers imagine a scenario where a TAS instruction
generated a page fault accessing the spinlock which could result in
incorrect behavior?  That would have to be the very first access of the
lock for a given transaction, otherwise the page would already be in
memory.  This is the only mid-instruction interrupt I can think of off hand.

I don't believe there is any interaction with hardware DMA that would be
relevant.  In any case our only driver at the moment that uses DMA is the
MACE Ethernet driver, correct?

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