On Tue, 25 May 1999, David A. Gatwood wrote:

> > The 5200/5260 at least are essentially Quadra 630's with a PPC accelerator.
> 
> That pretty much coincides with my info, except the model number, which I
> didn't have a clue about.  Thanks for the info there.  :-)
> 
> > The hardware map in Apples hardware docs for these is the same as the 630
> > with a PPC processor and a chip to translate between the 603/603e and the
> > mc68040 bus. I can't remember the url offhand but I recently found the
> > hardware documents for both machines on Apples web site
> 
> Same thing for the 53/52/5300 series machines.  Basically, it's an

D'oh!  I meant 53/62/6300 series machines.  ;-)


> IOW, I guess the question is: how many different VIA registers (ports,
> whatever) does the Quadra interrupt handling code have to read at the
> first stage?  Does it read several, each of which cascade into others, or
> does it read a single one, which cascades into several, which cascade into
> others?

I don't think I worded that very well....  In the non-Trailblazer (52xx,
etc.) PowerMacs, the interrupt handler reads a single master interrupt
flag register.  If certain bits are set, it reads other similar flag
registers. The question, then, is whether such a master register exists or
whether you have to check each of the VIA ports individually, followed by
each of the other IO subsystems that don't cascade into a VIA.... Anybody? 
:-)


Later,
David

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