Subject: Re: silo overflows
To: None <khym@bga.com>
From: Ken Nakata <kenn@synap.ne.jp>
List: port-mac68k
Date: 09/23/1998 09:45:26
On Tue, 22 Sep 1998 13:47:29 -0500 (CDT), Dave Huang wrote:
> 
> Do we _have_ to use /16 mode? It's been many years since I did anything
> with the SCC, but I seem to remember there being /1, /2 and /4 modes also?
> There was some limitation though... they only work for the synchronous
> modes or something?

Synch mode has no problem at all with /1 mode, since sample timing is
externally fed.  In a perfect world, asynch mode could have used /1
mode as well, but in the real world, things could get ugly when you
sample your input signal right at the signal edge when it's changing
its voltage level.  So, SCC samples the input twice (/2 mode), four
times (/4 mode) or 16 times (/16 mode) during one bit period (= 1/bps;
e.g. 1/57600 second), instead of just once (/1 mode).  Needless to
say, the more you sample, the more reliable edge detection you get.

So, I guess you could use /4 mode or even /2 mode by sacrificing a bit
of reliability.

Right, Bill?

Ken