Hello everybody!

I found some information in the linux-mac68k list.
Maybe someone could help this info.

Christoph Ewering         eweri@uni-paderborn.de
Husarenstrasse 48         Fon: 05254 12555
33104 Paderborn           www.uni-paderborn.de/Admin/eweri/


---------- Forwarded message ----------
Date: Mon, 9 Jun 1997 14:14:35 -0700 (PDT)
From: darknerd@best.com
Reply-To: linux-mac68k@rpelkey.bates.edu
To: linux-mac68k@rpelkey.bates.edu
Subject: [linux-mac68k] IIfx Stuff (MegaInfo)



OK, This is some more details that I'm familiar with (Bit,In/Out,Name,
Description):
   
VIA1 reg A:
  - 6 In   CPU.ID3
  - 4 In   CPU.ID2
  - 2 In   CPU.ID1
  - 1 In   CPU.ID0
VIA1 reg B (as per MacII family*): 
  - 7 In   /Par.Err   0 = parity error
      Out  vSndEnb    0 = sound enable
  - 6 Out  vSyncEnA   0 = vertical sync int enabled
  - 2 Out  rTCEnb     0 = RTC
  - 1 Out  rtcCLK     RTC Data-clock line
  - 0 I/O  rtcData    RTC Serial-data line
  * IIfx is only MacII that uses IOP for ADB.
VIA2 reg A (emulation)
  - 7 Out  v2RAM1     RAM-size bit 1
  - 6 OUt  v2RAM0     RAM-size bit 0
  - 5 In   v2RIQ6     Interupt from expasion slot $E
  - 4 In   v2RIQ5     Interupt from expasion slot $D
  - 3 In   v2RIQ4     Interupt from expasion slot $C
  - 2 In   v2RIQ3     Interupt from expasion slot $B
  - 1 In   v2RIQ2     Interupt from expasion slot $A
  - 0 In   v2RIQ1     Interupt from expasion slot $9
VIA2 reg B (emulation from OSS, BIU30, IOP)
  - 7 Out  v2VBL      60.15Hz interrupt request to VIA1
  - 6 In   v2SNDEXT   0 = plug is inserted into ext. sound jack
  - 5 In   v2TM0A     Transfer mode bit 0 acknowledge NuBus
  - 4 In   v2TM1a     Transfer mode bit 1 acknowledge NuBus
  - 2 Out  v2PowerOff 0 = Shut off power
  - 1 Out  v2BusLk    0 = NuBus transaction of locked out
  - 0 Out  v2CDis     0 = disable main processor's data/inst caches
Here are some other notes:
  There are IOPs for the SCC and SWIM/ADB.  You cannot access ADB through
VIA1 and you must go through the IOPs.  The IOPs registers are not mapped
to the processors memory and use a time-shared static memory accessed
through DMA channels.  Accessing SCC registers from the 68030 causes a bus
error.
  I completely understand ADB (well almost), but I do not understand
circuit diagrams.  I have a circuit diagram of the ADB interface on a IIfx
to the SWIM/ADB IOP.
Features...
  VIA1 functions handled by mutant chips:
   - IOP provides interface to ADB transceiver and computer
   - IOP provides state-control line SEL to floppy drive.
   - IOP controls whether SCC port A is used for sync or async I/O
   - IOP enables software to monitor SCC's Wait/Reqest output so that
     software can detect activity on serial port when interrupts are
     diabled
   - OSS monitors 60.15 Hz interrupt request (/VBLK) and interrupts 
     proccessor as necessary.
  VIA2 functions handled by rogue chips:
   - OSS performs an OR operation on six interrupt lines to generate
     /SLOTIRQ signal.
   - OSS monitors interrrupt lines from expansion slotes and stores in
     register and stores which slot generated interrupt.
   - OSS monitors interrupt lines from ASC (/SNDINT) and SCSI controller
     (SCSIIRQ) and interrrupts the processor as needed.
   - OSS provides power off signal (/POWEROFF) and shuts down processor.
   - OSS monitors signal (/SNDEXT) for external jack plugged into
     computer.
   - OSS checks parity if this is used.
   - OSS monitors Data Request line from SCSI DMA (SCSIDRQ) and can 
     interrupt processor when SCSI DMA is ready to transfer data.
   - BIU30 provides signal (/BUSLOCK) that blocks NuBus cards from 
     accessing main logic board.
   - BUI30 records status signals from NuBus (/TM0A and /TM1A).  The main
     processorcan read value a register in BIU30 to find out the values
     of those two signals    
Really SCSI things (features of SCSI DMA IC)
   - DMA bypass fopr 53C80 compatability.
   - Async 3 meg/sec
   - Automatic SCSI bus arbitration as well as program-controlled
     arbitration.
   - DMA transfers of 32bit longwords
   - support for misaligned data buffer addresses (nozero MOD 4)
   - hardware handshake mode (software-controlled data transfer with no
     polling for available bytes)
   - direct acesses to the whole shebang (32bit address memory lines)
   - block transfers of up to 4 gigs.

   Generally the main process sends control/command bytes one byte at a
   time, but with DMA this can be done 4 bytes at a time.

This is all the info I can gather up for right now.  Does anyone
understand how to get to the IOP DMA lines to through some bits in that
direction?  I can imagine that ADB is going to be a pain in the rear on
this machine.  SCSI should be easy because there's a compatability mode
for non-handshaking tranactions.

enjoy,
  Joaquin