Subject: Re: more on understanding caches.
To: Toru Nishimura <nisimura@itc.aist-nara.ac.jp>
From: Soren S. Jorvang <soren@wheel.dk>
List: port-m88k
Date: 07/28/2000 08:03:09
On Mon, Jul 24, 2000 at 11:38:16AM +0900, Toru Nishimura wrote:
> > Invalidate
> > Writeback
> > Writeback+Invalidate
> 
> It was the initial thought of mine, indeed.  However, I hesitate to
> supercede and conceal 'write-thru' notion with the term of
> 'write-back' although it's reasonable to construct cache operations
> in write-back centric fashion because write-thru is mostly invible
> for kernel logics.

Ok. We could just s/writeback/sync/ in the above for slightly more
generic names, and still reflect common hardware organisation.


-- 
Soren