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Re: Some fixes for m68k users (incl/ for FPU emulation)



> On Nov 1, 2026, at 6:12 AM, Romain Dolbeau <romain%dolbeau.org@localhost> wrote:
> 
> I haven't looked at pmap_68k so it might be OK already; please make
> sure U0/U1 aren't used for internal purposes - they are exposed on
> external pins so could have an impact on the hardware (even if in r
> practice almost nobody used them), and they are needed to "properly"
> support SMP on MC68040 (they are used to indicate the level of type of
> snooping to use for the data in that page).

My new pmap module uses the following PTE bits:

/*
 * Abstract definitions for PTE bits / fields.  C code will compile-time-
 * assert the equivalencies that we assume.
 *
 * N.B. assumes exclusive use of short descriptors on 68851.
 */
#define PTE_VALID       PTE40_RESIDENT  /* == DT51_PAGE */
#define PTE_WP          PTE40_W         /* == PTE51_WP */
#define PTE_M           PTE40_M         /* == PTE51_M */
#define PTE_U           PTE40_U         /* == PTE51_U */
#define PTE_PVLIST      PTE40_G         /* unused on '51, don't use PFLUSHxN */
#define PTE_WIRED       PTE40_UR        /* unused on '51 */

In mmu_40.h, I have some additional commentary that goes along with it:

/*
 * The PTE format for L3 tables.
 *
 * Some notes:
 *
 * - PFLUSH variants that specify non-global entries do not invalidate
 *   global entries.  If these PFLUSH variants are not used, then the G
 *   bit can be used as a software-defined bit.
 *
 * - The UR bits are "reserved for use by the user", so can be
 *   used as software-defined bits.
 *
 * - The U0 and U1 "User Page Attribute" bits should *not* be used
 *   as software-defined bits; they are reflected on the UPA0 and UPA1
 *   CPU signals if an external bus transfer results from the access,
 *   meaning that they may have system-specific side-effects.
 */

…and note:

#define PTE40_UR_x      __BIT(12)       /* User Reserved (extra avail if 8K) */

…you get an extra software-defined bit if you use 8K pages.

-- thorpej



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