kiyohara@kk.iij4u.or.jp wrote:

> Do you think that it should be able to access the kernel to be
> transparently by [id]tt[01] setting?
> If it is possible to access to be transparently, the frequency of MMU
> fault can be decreased, and it access it safely the code and stack at
> interrupt.  For instance, range of 0x00000000-0x01000000. 

I don't know whether there is any recommendation of RAM mappings
on ColdFire, but if RAM could be allocated at other than 0x0
on physical address, I don't think we can use transparent mappings.

For example, hp300 machines have RAM allocated from
0xfffffff (which is the lowest address on big endian?)
to higher (i.e. smaller) address.

It's better to use 1M mappings if you consider to reduce
TLB miss, I guess.

(Does i386 still have 4M kernel page option?
 i.e. is sys/arch/i386/conf/largepages.inc still vaild?)
---
Izumi Tsutsui