Hi! all,


CFV4e (68K/ColdFire V4e) has 64-entries TLBs on MMU.  It can config
only 1, 4, 8K, and 1M.  I think that MMU fault is frequently except.
However, it has register [id]tt[01] (ACR0-ACR3) as well as MC680x0.

Do you think that it should be able to access the kernel to be
transparently by [id]tt[01] setting?
If it is possible to access to be transparently, the frequency of MMU
fault can be decreased, and it access it safely the code and stack at
interrupt.  For instance, range of 0x00000000-0x01000000. 

Thanks,
--
kiyohara