Hi Todd,

> On Wed, 11 Sep 1996, der Mouse wrote:
> 
> : Are there no 68k family CPUs that can interrupt partway through an
> : instruction?  I know some VAX instructions are interruptible, but the
> : 68k doesn't have the monster instructions like MOVTUC the VAX does.
> 
> The 68k has no interruptible instructions native to the CPU itself,
> excepting perhaps some extensions found in the 68040+ (is MOVE16
> interruptible?).  Coprocessor (particularly FPU) instructions may or may not
> be interruptible; take a gander at the 'busy stack frame' spit out by the
> FPU by a FSAVE when one such instruction is interrupted. 
> 
> The 68k has a couple special instructions which go even a bit further than
> the uninterruptible instruction dogma; look at CAS and CAS2 (sigh, we lost
> the latter in the 68060), 

You forgot the CAS on unaligned addresses. This is emulated, too.

"We lost CAS2" is not true, however. The OS's software emulation of CAS2 
(and you forgot misaligned CAS, btw) has to ensure the uninteruptibility, 
if desired, by locking the (up to) two pages in memory before emulation, 
and unlocking them (if they were locked) afterwards; I think the emulation 
code does set (and clear afterwards) the BUS LOCK signal of the CPU in software 
at the appropriate times.

My integration of the code does not do the page lock stuff yet. IMO, its
cheaper if 


- for user space semaphores: the WHATWASIT_HASSEMAPHORE flag of the mmap() 
call used ensures that the region is locked in memory (if used on the 68060 cpu
only), which takes all the complicated and lengthy checks & actions out
of the instruction emulation, 

- for system space semaphores, the system just places the variables at
appropriate boundaries and only uses CAS.

Note that both are only needed on Multicpu systems. Singlecpu systems
shouldn't need CAS/CAS2/TAS in the first place; BSET #n, _someaddress is
uninteruptible and returns the old value of the bit, which should be
enough for any cheap semaphore code you would want.

Regards,
	Ignatios Souvatzis