Re: ehci panic

[Patrick Welche <prlw1%cam.ac.uk@localhost>]

On Mon, Jul 17, 2017 at 09:40:18PM +0200, Jarom?r Dole?ek wrote:
> The constant is wrong. There are 4 bits for number of companion devices, so
> maximum is actually 15.
> 
> Can you try kernel with this change?

It gets further!

ehci0 at pci0 dev 29 function 7: vendor 8086 product 24cd (rev. 0x03)
ehci0: interrupting at irq11
panic: kernel diagnostic asserition "(reg & 0x3) == 0" failed: "file "/usr/src/sys/arch/x86/pci/pci_machdep.c", line 621

(show registers seems to show the state after writing the nice panic message)

ch_voltag_convert_in()
pci_conf_read(0,8000ef00,e2,c01a2e1f,c1fb0d24,20,b,8086,c1fb2808,c150acbc)
ehci_get_owndership()
ehci_pci_attach()

How does
pci_conf_read(0,8000ef00,e2,c01a2e1f,c1fb0d24,20,b,8086,c1fb2808,c150acbc) 
map to pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
?

Guessing reg == 0xb == 1011 => 1011 & 0011 != 0


If I boot by using userconf disable ehci*, pcictl tells me:

PCI configuration registers:
  Common header:
    0x00: 0x24cd8086 0x02900000 0x0c032003 0x00000000

    Vendor Name: Intel (0x8086)
    Device Name: 82801DB USB EHCI Controller (0x24cd)
    Command register: 0x0000
      I/O space accesses: off
      Memory space accesses: off
      Bus mastering: off
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x0290
      Immediate Readiness: off
      Interrupt status: inactive
      Capability List support: on
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: serial bus (0x0c)
    Subclass Name: USB (0x03)
    Interface Name: EHCI (0x20)
    Revision ID: 0x03
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x00
    Cache Line Size: 0bytes (0x00)

  Type 0 ("normal" device) header:
    0x10: 0x00000000 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000000 0x00011179
    0x30: 0x00000000 0x00000050 0x00000000 0x000004ff

    Base address register at 0x10
      not implemented
    Base address register at 0x14
      not implemented
    Base address register at 0x18
      not implemented
    Base address register at 0x1c
      not implemented
    Base address register at 0x20
      not implemented
    Base address register at 0x24
      not implemented
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x1179
    Subsystem ID: 0x0001
    Expansion ROM Base Address: 0x00000000
    Capability list pointer: 0x50
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x04 (pin D)
    Interrupt line: 0xff

  Capability register at 0x50
    type: 0x01 (Power Management)
  Capability register at 0x58
    type: 0x0a (Debug Port)

  PCI Power Management Capabilities Register
    Capabilities register: 0xc9c2
      Version: 1.1
      PME# clock: off
      Device specific initialization: off
      3.3V auxiliary current: 375 mA
      D1 power management state support: off
      D2 power management state support: off
      PME# support D0: on
      PME# support D1: off
      PME# support D2: off
      PME# support D3 hot: on
      PME# support D3 cold: on
    Control/status register: 0x0000
      Power state: D0
      PCI Express reserved: off
      No soft reset: off
      PME# assertion: disabled
      Data Select: 0
      Data Scale: 0
      PME# status: off
    Bridge Support Extensions register: 0x00
      B2/B3 support: off
      Bus Power/Clock Control Enable: off
    Data register: 0x00

  Debugport Capability Register
    Debug base Register: 0x2080
      port offset: 0x0080
      BAR number: 1

  Device-dependent header:
    0x40: 0x00000000 0x00000000 0x00000000 0x00000000
    0x50: 0xc9c25801 0x00000000 0x2080000a 0x00000000
    0x60: 0x007f2020 0x00000000 0x00000001 0xc0000000
    0x70: 0x00010000 0x00000000 0x00000000 0x00000000
    0x80: 0x00000000 0x00000001 0x00000000 0x00000000
    0x90: 0x00000000 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x003f0010
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x001fbf78 0x00008388 0x00000f60 0x00000006


Cheers,

Patrick