Subject: Re: ioapic and interrupt lines
To: None <email@example.com>
From: Takayoshi Kochi <kochi@NetBSD.org>
Date: 09/12/2005 10:43:43
Hi Manuel, Frank
> >Does anyone know if an interrupt > 31 is valid on current i386 hardware ?
> >>From what I can see in our i386 code, it 0-15 for legacy more, or
> >0-31 for ioapic.
> Hey Manuel,
> That depends on the ioapic. The theoretical maximum is 255, since 8 bits
> in register 0x01 of an ioapic determine the maximum size. I've not seen
> ioapics with more than 24 lines for normal systems, though.
The argument is only valid for *one ioapic*.
> What's your context? There's also the ACPI "global interrupt number",
> which can be bigger, since it assigns a unique number to all interrupts
> in the system. That can certainly be bigger than 31, though it's
> software only.
to clarify things more... (just FYI)
If there are more than 1 ioapics in a system, there can be
more than 255 *interrupt lines*.
ACPI can report multiple ioapics in its MADT table,
whose entry describes the following about an ioapic:
1) base Global System Interrupt (GSI) number
2) # of interrupt input pins
3) base addr of memory-mappied ioapic register, etc...
the GSI number (1 + 2) for each interrupt pin is unique in a system.
from ACPI spec, the upper limit of GSI number isn't clear but at
least it can be 32 bit-wide.
The ioapics will translate the input interrupts into *vector number*
with which x86 cpus can identify an interrupt source. The vector number
is upper bounded to 255 by the cpu's spec.
Therefore more than 255 interrupt sources (practically more than
192 or so, because some of them are used for legacy interrupts and
IPI etc.) mean some of them have to be shared, though.
I don't think such a big configuration is practical, I'm just saying
that it's possible...