woods@weird.com (Greg A. Woods) writes:

> [ On , October 22, 2002 at 17:15:27 (-0400), Nathan J. Williams wrote: ]
> > Subject: Re: Offtopic, Mainboard recommandation
> >
> > With sufficently wide DIMMS, the chipset (AMD 760MPX) supports
> > generating ECC data on write and checking ECC data on reads. If the
> > right bit in the configuration is enabled, a fault is generated when
> > an error (single or multibit) is detected. The fault is a PCI SERR#,
> > which the southbridge can turn into a processor NMI).
> 
> Ah ha!  This is indeed more or less how I've come to understand many
> such motherboards work.  What I'm less certain of is how many (or more
> specifically exactly which models) have the NMI generation enabled by
> default, and I'd like to learn how to check if it's enabled and how to
> enable it if it's not already enabled by the BIOS.

Given the history of PCs, I'd be rather surprised if anything
defaulted to having this enabled, as opposed to depending on the OS to
set it up.

Knowing how to enable it should be a matter of grovelling through the
chipset documentation, probably mostly Intel's.

> I'm guessing that NetBSS/i386 as yet has no generic support for ECC
> reporting at all, is that right?

Correct.

> If I can do anything to help with getting this code in place and tested
> on a wider variety of i386 machines then please do let me know!  In fact
> I currently have an Elite Group Computer Systems P6FX1-A P-Pro
> motherboard that occasionally triggers an NMI and I'm keen to diagnose
> the cause of this and if it's due to ECC to know how often the corrected
> error events happen.

If you let me know what the chipset on that board is, I'll have a look
at supporting when I do the work for the AMD MPX+.

        - Nathan