On Sun, Feb 17, 2002 at 10:20:23PM +0000, David Laight wrote:
> 
> I haven't looked at the code in question :-) but it might be suffering
> from delayed writes.  Every x86 since the 386, most recent (< 10
> year) sparc chips, any PCI bus system, StrongArm etc doesn't do
> write (inc IO) cycles (even uncached ones) synchronously.  Basically
> the address and data are put through a FIFO, if you need the write to
> happen, then you must force the data out of the FIFO.  The only way
> that clear ALL the FIFOs is to issue a read cycle that requests the
> same address as a queued write.  Depending on the system this MAY
> force all previous writes to 'memeory'.

Actually I don't think it is that bad. Intel does not need to risk
compatibility doing such kind of optimizations. Even if x86 does
indeed queue IO writes, there is no reason to hold data in IO FIFO
for longer than, say, 100 cycles. Same holds for PCI controllers.

Other architectures usually provide some way to flush write buffer.
Alpha's wmb (as opposed to mb) (among other functions) starts clearing
the FIFO. Additionally it is guaranted to be flushed after finite amount
of time (for example, 256 cycles on 21164).

> So maybe the delay is in the spec.  Doing a serier of IOW (to a slow
> ISA device) is a reasonable way on ensuring your delay isn't cpu
> speed dependant.  However you do need to force the writes to happen.

But why would lack of delays just slow things down and not break entirely?
Wojciech, you haven't got any wdc driver error messages on console, have you?


Greetings,


	Witold J. Wnuk