In message <Pine.LNX.4.33.0111091813120.1300-100000@denkigama.nat.shibuya.blink
.co.jp>, you write: 

-> Well, inspired by PR11299, I've had a slightly closer look at the PCI BIOS
-> problems in my libretto. Essentially, it generates a uvm fault whilst
-> in the PCIBIOS "fetch interrupt table" code. It dies with:
-> 
->     uvm_fault(0xc04826a0, 0x2000, 0, 1) -> e
->     kerenel: page fault trap, code=0
->     Stopped in pid 0 (swapper) at 0xc056ae8b: cmpb %cs:0x2db(%si),%al
-> 
-> At this point, %cs is 0x8, and %esi is 0xc0550000.
-> 
-> Unfortunately, I'm confused by all the different modes and segment
-> registers and god knows what in this stupid processor, so I'm wondering
-> just what location this is trying to access. Since I did a PCIBIOS call,
-> am I now in 16-bit mode at this point? Or do PCIBIOS calls happen in
-> 32-bit mode? Is it really using just %si, and ignoring the upper half
-> of %esi, or is it using all of %esi? And, in the end, just what memory
-> location is it trying to access?

I've now forgotten all I knew since I wrote up 11299, but I believe you're
running the code in 32-bit mode (I believe PCIBIOS calls are all 32bit), 
and it seems you're also still in protected mode (in 11299, the pnpbios 
calls are done in 16-bit real mode) as the kernel actually catches the 
trap.

I don't recall enough x86 assembly, but I'd hazard a guess that you only
need to worry about %si not %esi; what address you're actually trying to
read depends on how %cs is interpreted in this case, and that part I'm not
knowledgeable enough on to even guess (mmm, repressed memory 8-).

--rafal

----
Rafal Boni                                                  rafal@mediaone.net